1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly, to a memory block of a semiconductor memory apparatus that has an open bit line structure.
2. Related Art
A conventional dynamic random access memory (DRAM) includes a plurality of memory cells each of which has one transistor and one capacitor to store data. Each of the memory cells is connected to a word line and a bit line, and the word line is connected to a sub-word line driver and the bit line is connected to a bit line sense amplifier. The bit lines constitute bit line pairs, and data whose phases are opposite to each other is carried to each of the bit line pairs. Each of the bit line pairs is connected to a local data bus pair and it is determined whether each bit line and each local data bus are connected to each other according to a column selection signal that is generated by decoding a column address.
Hereinafter, a conventional memory block of a semiconductor memory apparatus will be described with reference to FIGS. 1 and 2.
FIG. 1 is a first exemplary view illustrating a configuration of the conventional memory block of a semiconductor memory apparatus, which exemplifies one of a plurality of cell mats that are included in the memory block and sense amplifiers disposed at both ends of the cell mat.
As shown in FIG. 1, the conventional memory block of the semiconductor memory apparatus includes a first cell mat 1 and first to fourth sense amplifiers 2-1 to 2-4 that are disposed at both ends of the first cell mat 1.
Four bit line pairs BL1 and /BL1 to BL4 and /BL4 are sequentially disposed in the first cell mat 1. Memory cells are disposed at intersections of the four bit line pairs BL1 and /BL1 to BL4 and /BL4 and six sub-word lines SWL1 to SWL6, respectively. In FIG. 1, a sub-word line driver block is not shown.
The first sense amplifier 2-1 is connected to the first cell mat 1 through the first bit line pair BL1 and /BL1. The second sense amplifier 2-2 is connected to the first cell mat 1 through the second bit line pair BL1 and /BL2. The third sense amplifier 2-3 is connected to the first cell mat 1 through the third bit line pair BL3 and /BL3. The fourth sense amplifier 2-4 is connected to the first cell mat 1 through the fourth bit line pair BL4 and /BL4.
In response to first and third column selection signals ‘YS’<1,3>, a first column selecting unit 3-1 connects the first bit line pair BL1 and /BL1 that is connected to the first sense amplifier 2-1 and a first local data bus pair LI01 and /LI01, and the third bit line pair BL3 and /BL3 that is connected to the third sense amplifier 2-3 and a third local data bus pair LI03 and /LI03. In response to second and fourth column selection signals ‘YS’<2,4>, a second column selecting unit 3-2 connects the second bit line pair BL2 and /BL2 that is connected to the second sense amplifier 2-2 and a second local data bus pair LI02 and /LI02, and the fourth bit line pair BL4 and /BL4 that is connected to the fourth sense amplifier 2-4 and a fourth local data bus pair LI04 and /LI04.
In order to increase the integration of the memory block of the semiconductor memory apparatus, the conventional semiconductor memory apparatus implements a memory block having an open bit line structure. That is, each of the bit line sense amplifiers is connected to a different cell mat through the positive bit line BL and the negative bit line /BL. As a result, in the arrangement of memory cells in the cell mats, extra space is removed, allowing dense arrangement of the memory cells.
FIG. 2 is a second exemplary view illustrating a configuration of the conventional memory block of the semiconductor memory apparatus according to the related art, which illustrates the memory block having an open bit line structure. Specifically, FIG. 2 exemplifies two mats among a plurality of cell mats included in the memory block and sense amplifiers that are disposed between the two cell mats.
As shown in FIG. 2, the conventional memory block of the semiconductor memory apparatus includes a first cell mat 4, a second cell mat 5, and first to fourth sense amplifiers 6-1 to 6-4 that are disposed between the first cell mat 4 and the second cell mat 5.
In the first cell mat 4, four bit line pairs BL1 and /BL1 to BL4 and /BL4 are sequentially disposed, and memory cells are respectively provided at intersections of the four bit line pairs BL1 and /BL1 to BL4 to /BL4 and the six sub-word lines SWL1 to SWL6. The second cell mat 5 has the same structure as the first cell mat 4 except for the arrangement order of the four bit line pairs /BL1 and BL1 to /BL4 and BL4. In FIG. 2, a sub-word line driver block is not shown.
The first sense amplifier 6-1 is connected to the first cell mat 4 through the positive first bit line BL1 and to the second cell mat 5 through the negative first bit line /BL1. The second sense amplifier 6-2 is connected to the first cell mat 4 through the positive second bit line BL2 and to the second cell mat 5 through the negative second bit line /BL2. The third sense amplifier 6-3 is connected to the first cell mat 4 through the positive third bit line BL3 and to the second cell mat 5 through the negative third bit line /BL3. The fourth sense amplifier 6-4 is connected to the first cell mat 4 through the positive fourth bit line BL4 and to the second cell mat 5 through the negative fourth bit line /BL4.
The first to fourth sense amplifiers 6-1 to 6-4 operate in response to a bit line equalize signal ‘bleq’. When the bit line equalize signal ‘bleq’ is disabled, the first to fourth sense amplifiers 6-1 to 6-4 amplify the positive bit line and the negative bit line or the negative bit line and the positive bit line at a level of a first sense amplifier power supply voltage (in this case, RTO voltage RTO) to perform a high-level sensing operation and a level of a second sense amplifier power supply voltage (in this case, SB voltage SB) to perform a low-level sensing operation. Meanwhile, when the bit line equalize signal ‘bleq’ is enabled, the first to fourth sense amplifiers 6-1 to 6-4 precharge the positive bit line and the negative bit line with a level of a bit line precharge voltage Vblp.
Although not shown in the drawing, sense amplifiers, which are connected to the first cell mat 4 through the negative first to fourth bit lines /BL1 to /BL4, may exist at the left side of the first cell mat 4. Further, sense amplifiers, which are connected to the second cell mat 5 through the positive first to fourth bit lines BL1 to BL4, may exist at the right side of the second cell mat 5.
In response to first to fourth column selection signals ‘YS’<1:4>, a first column selecting unit 7-1 connects the positive first to fourth bit lines BL1 to BL4 that are connected to the first cell mat 4 and the positive first to fourth local data buses LI01 to LI04. In response to the first to fourth column selection signals ‘YS’<1:4>, the second column selecting unit 7-2 connects the negative first to fourth bit lines /BL1 to /BL4 that are connected to the fifth cell mat 5 and the negative first to fourth local data buses /LI01 to /LI04.
As described above, the conventional memory block of the semiconductor memory apparatus includes four sense amplifiers in order to amplify the four positive bit lines of the first cell mat 4 and the four negative bit lines of the second cell mat 5. That is, the conventional semiconductor memory apparatus includes the same number of sense amplifiers as bit line pairs. However, as is well known, each of the sense amplifiers includes several transistors and occupies a wide area, which makes it difficult to achieve high integration of the memory block. As shown in FIG. 2, due to the arrangement of the sense amplifiers, extra space is generated in each of the sense amplifier blocks, which results in lowering the integration of the memory block.
That is, as described above, in order to achieve the high integration of the semiconductor memory apparatus, efficient space arrangement of the memory block is required. However, because the conventional memory block requires sense amplifiers corresponding to bit line pairs, it is difficult to secure sufficient area margin in order to increase the integration of the memory block. Further, extra space is generated between the sense amplifiers, which results in lower spatial utilization efficiency.